This invention relates to an integrated circuit, comprising a D-type master/slave flipflop comprising:
a bistable master element connected between two supply voltage terminals and having a first data input for receiving data,
control means having a control signal input for erasing or enabling writing into the master element under control of a control signal;
a bistable slave element connected between two supply terminals and having a second data input connected to a data output of said master element.
The invention is used, for example, a comparator which is part of an analog-to-digital converter which is referred to as a parallel converter in which an analog input signal is applied to the inputs of several parallel comparator circuits in order to obtain a digital output signal. The input voltage is compared in said circuits with a reference voltage which differs for each comparator circuit. The output signals of the comparator circuits are converted into a digital output signal by means of a decoding device. Analog converters often comprise a flip-flop as described above.
A circuit of this kind is known, inter alia from European Patent Application No. 85 20 1742.5, which corresponds to U.S. Pat. No. 4,649,293 (3/10/87).
The cited U.S. Pat. No. describes a clocked voltage comparator which comprises a Delay-type master/slave flip-flop. The clocked comparator comprises:
an acquisition or comparison stage which serves to compare an analog input voltage (V.sub.IN) with an analog reference voltage (V.sub.REF) and to supply the result of said comparison as an intermediate signal (V.sub.M) and its complement (V.sub.M). An amplifier stage amplifies the logic states of the intermediate signal. A first and a second latching stage are coupled to the comparison stage and the amplifier stage, respectively, for generating and storing the logic states determined by the signals from the comparison stage and the amplifier stage. Each latching stage comprises a differential transistor pair having a common terminal connected to ground. A further differential transistor pair is arranged in parallel with the last-mentioned transistor pair and is controlled by a clock signal C for the first latching stage and by its complement C for the second latching stage. The comparison stage and the amplifier stage are also controlled by the clock signal C and the latching stages are each coupled to the comparison stage and the amplifier stage, respectively, by means of load resistors.
The known comparator operates in two periods. In a first period acquisition of the information by the first differential pair takes place. This acquisition is effected at the drain of the transistors of the first differential pair of the first latching stage when the clock or control signal is high.
At that instant the output signals of the memory stage, being available at the gate electrodes of the transistors of the bistable circuit and forming the output signals of the comparator, appear as signals whose states are both nearly zero. Former information available at the gate electrodes is erased.
During a second period, when the clock or control signal becomes low or zero again, the decision and storage function is performed, i.e. the signals which are available at the gate electrodes of the bistable circuit and which were previously both nearly zero then become complementary.
Thus, each time when the clock signal is high, the output signals of the comparator are erased and both become approximately zero and at that time these output signals do not furnish information. This is a problem in applications where this information is needed at any moment.
It is known from the state of the art, i.e. from the cited U.S. patent, that this problem can be solved by utilizing a master-slave structure, i.e. by associating two comparators in the way that has been set forth hereinabove. This structure enables the storage of the information during the acquisition phases.
However, this known structure necessitates the use of a large number of components, which is a drawback when large scale integration is desired. On the other hand, this solution also necessitates the use of a complementary clock signal which is always difficult to realize when a strictly complementary signal is to be obtained.